Mixers and modulators are devices which modulate low frequency signals or baseband signals onto a higher frequency carrier for transmission purposes. One type of modulators is an AM (amplitude modulation) modulator, where the lower frequency data is modulated onto amplitude of the higher frequency carrier. The operation of such an AM modulator can be depicted as a simple multiplication of the lower and higher frequency signals. The AM modulator is also referred to as an AM mixer. A typical AM modulator has a local oscillation (LO) signal input to which the carrier signal (i.e., local oscillation signal) is applied, a signal input to which the low frequency signal is applied, and an output for providing a modulated signal. A particular disadvantage of the basic AM modulator is that the output signal contains the higher frequency carrier signal, which carries no useful information and uses transmission power.
A modified form of modulator, known as a double sideband suppressed carrier (DSBSC) modulator is shown in FIG. 1A. The DSBSC modulator is also referred to as a DBM (double balanced mixer). The illustrated DSBSC modulator has current source 101, six transistors M1 through M6, a pair of balanced input terminals 102, 103 to which a baseband signal is applied, a pair of balanced input terminals 104, 105 to which a local oscillation (LO) signal is applied, and a pair of balanced output terminals 106, 107 from which the modulated signal is delivered as a current output. Transistors M1 through M3 constitute a first AM mixer while transistors M4 through M6 constitute a second AM mixer. One end of current source 101 is connected to the ground potential point, and sources of transistors M1, M4 are commonly connected to the other end of current source 101 so that the first and second AM mixers share current source 101. In the first AM mixer, a gate of transistor M1 is connected to non-inverting input terminal 102 of the baseband signal, and a drain of transistor M1 is connected to sources of transistors M2, M3. Gates of transistor M2, M3 are connected to inverting input terminal 105 and non-inverting input terminal 104, respectively, and drains of transistors M2, M3 are connected to inverting output terminal 107 and non-inverting output terminal 106 of this DSBSC modulator, respectively. In the second AM mixer, a gate of transistor M4 is connected to inverting input terminal 103 of the baseband signal, and a drain of transistor M4 is connected to sources of transistors M5, M6. Gates of transistor M5, M6 are connected to non-inverting input terminal 104 and inverting input terminal 105, respectively, and drains of transistors M5, M6 are connected to inverting output terminal 107 and non-inverting output terminal 106 of this DSBSC modulator, respectively.
This type of modulator can suppress the carrier signal at the output by cancelling the local oscillation components at the two AM mixer outputs, which is possible because the two oscillator signals are applied in opposing phases. This arrangement is commonly used because of the increased efficiency.
As well known to those skilled in the art, an example of applications of the DSBSC modulator is a quadrature (IQ) modulator which is used for orthogonal amplitude modulation and/or demodulation. As shown in FIG. 1B, a typical quadrature modulator comprises signal input terminals 111, 112 for first and second signals, respectively, LO input terminal 113 for receiving a local oscillation (LO) signal, phase shifter 114 for shifting phase of the local oscillation signal by 90 degrees, first and second DSBSC modulators 115, 116 for receiving the first and second signals, respectively, combiner 117 for adding the outputs of both DSBSC modulators 115, 116, and RF output terminal 118 connected to the output of combiner 117. The local oscillation signal is directly supplied to first DSBSC modulator 115 from LO input terminal 113 while second DSBSC modulator 116 receives the local oscillation signal through phase shifter 114. In such a quadrature modulator, the first signal corresponds to an I (in-phase) component of the output modulated signal while the second signal corresponds to a Q (quadrature) component. Therefore, the first signal is also referred to as an I signal and the second signal a Q signal.
A problem with the fabrication of DSBSC modulators arises due to the carrier suppression requirement. This typically arises due to unavoidable manufacturing tolerances of the two AM mixers, which are usually implemented as parts of a monolithic chip such as a semiconductor integrated circuit device. If there is imperfect matching of the transistors in the DSBSC modulator, then not only the sidebands of the modulated signal are transmitted, but also a leak at the local oscillator frequency, equivalent to a DC offset at the output of the DSBSC modulator is transmitted. Such a carrier leak is undesirable as it makes it difficult to capture the phase of the transmitted signal during demodulation, and can also cause undesired interference with other communications.
Efforts to fix this problem can involve adding a configuration for applying a static DC offset to the modulator input in order to cancel the carrier signal. For example, Japanese Patent Laid-open Application No. 2002-198745 (JP, P2002-198745A) discloses an arrangement in which a DC offset voltage is applied to a local oscillation input terminal. However this approach cannot account for the long-term drift in the circuit parameters and operating temperature.
An additional approach is to increase the physical size of the transistors in the circuit to reduce relative variations in the parameters of the transistors, but this is unsuitable for high frequency circuitry as the increased parasitic capacitance reduces the gain at the carrier frequency. In addition, special layout techniques can also be used to cancel the process error gradient across the chip surface, but in practice this method increases the circuit area and cost and may still not give enough carrier suppression.
In U.S. Pat. No. 5,012,208 issued to Makinen et al., a solution for the problem of local oscillation signal leak (i.e., DC offset) in a quadrature modulator is disclosed. FIG. 2 illustrates an arrangement of the circuit of Makinen et al. which solves the problem of quadrature modulator DC offset cancelling. In this circuit, an output of quadrature modulator 121 is supplied to amplifier 122, and the output of amplifier 122 is supplied to RF output terminal 123 and power measuring circuit 124. Power measuring circuit 124 provides an envelope of the transmitted RF signal from amplifier 122. The output of power measuring circuit 124 is supplied to amplifier 125 through high pass filter 126. Linear correlators 127, 128 correlate the I (in-phase) and Q (quadrature) input signals received at input terminals 129, 130 with the output signal of amplifier 125, respectively. The outputs of correlators 127, 128 are integrated by integrators 131, 132. Subtractor 133 subtracts the output of integrator 131 from the I input signal received at input terminal 129 and supply the result to quadrature modulator 121 as an I signal. Similarly, subtractor 134 subtracts the output of integrator 132 from the Q input signal received at input terminal 130 and supply the result to quadrature modulator 121 as a Q signal.
This approach calculates error signals using the envelope of the transmitted RF signal and the time domain signals at the I and Q inputs. By correlating the envelope signal with the input signals in the linear correlators, and integrating the results, error signals are extracted to compensate the modulator offsets. The two error signals are separately derived from the single envelope signal due to the correlation over a long time period between the average DC level of the I and Q input signals and the average peak level of the envelope signal in the I and Q phase domains.
An essential component of the system of FIG. 2 is a linear multiplier (correlator) with a very low DC offset. Any large DC offset of this component will prevent the full cancellation of the DC offsets of the modulator. Typically, the system of FIG. 2 would be difficult to implement purely in the analog domain due to the requirement of a linear analog multiplier with a low DC offset. Such circuits tend to be complicated and therefore difficult to implement with the required accuracy for this application. Therefore the system of FIG. 2 would be expected to be implemented in the digital domain apart from the section of the loop from the quadrature modulator to the power measuring circuit and the amplifier. Implementing the system in the digital domain requires an ADC (analog-to-digital converter) to convert the signal at the amplifier output. However, the provision of the ADC carries much production overhead and implementation cost.
Therefore, it is desired to provide an error calculation circuit which generates an error compensation signal to be applied to a mixer or a modulator, has a simple circuit structure, and is easily manufactured.
Japanese Patent Laid-open Application No. 9-307596 (JP, 9-307596, A) discloses an arrangement in which a cancel carrier signal is generated and added to the modulated carrier signal.
Japanese Patent Laid-open Application No. 2000-261252 (JP, P2000-261252A) discloses a distortion compensation circuit for an RF power amplifier in which a result of envelope detection of an input signal is used for compensating distortion components in an output of the amplifier.
Japanese Patent Laid-open Application No. 10-70582 (JP, 10-070582, A) discloses an arrangement for reducing the leak carrier in a quadrature modulator by generating a beat signal between a modulated signal and an local oscillation signal, detecting the beat signal and generating a DC offset signal (i.e., error compensation signal) based on the detection result.
Japanese Patent Laid-open Application No. 11-220506 (JP, 11-220506, A) discloses an arrangement for reducing the leak carrier in a quadrature modulator output. In this arrangement, a local oscillation signal is doubled in frequency and separated to quadrature phase components. These phase components are modulated and then combined.
Japanese Patent Laid-open Application No. 2003-125014 (JP, P2003-125014A) discloses a quadrature modulator in which DC offset voltages are added to I and Q balanced input signals.